The present invention relates generally to digital delay circuits. More particularly, the present invention relates to a digital delay circuit that compensates for practical variations in manufacturing processes and operating conditions.
Many digital circuits utilize delay elements designed to delay a digital signal by either an absolute amount or by a defined fraction of its clock period. In practice, such delay elements can be utilized in a variety of applications, e.g., frequency doublers and parallel data transfer. A conventional digital delay element may include a series of buffer elements, each having an incremental delay associated therewith. For example, if a clock signal with a period of 3.2 nanoseconds needs to be delayed by 800 picoseconds, then the clock signal can be delayed with an appropriate number of buffers to arrive at a nominal delay of 800 picoseconds. In real world applications, however, variations in process, temperature, voltage, and other environmental conditions can result in an actual delay that ranges between 500 picoseconds to 1100 picoseconds. Unfortunately, some applications cannot tolerate such a high amount of imprecision in the delay.
One known solution to the above problem is to screen and discard devices having actual delay characteristics that fall outside of the specified limits. Depending upon the manufacturing process and external conditions, such screening can potentially result in a large yield loss.
In a system in which a clock delay is utilized to latch digital data, a clock recovery unit may be employed to derive the clock from the data or from a signal having the same timing as the data. While this approach avoids the need to have an independent clock signal with the specified delay, it can be costly in terms of power and physical circuit area.
Another prior art approach utilizes a high speed shift register to delay an external clock signal. This solution typically requires a relatively high amount of operating power, and it introduces the problem of metastability (the metastability issue can be addressed at the expense of additional operating power).
Accordingly, it would be desirable to have a digital delay circuit that provides a narrow range of practical delay values across a variety of process and/or environmental conditions.
A digital delay circuit according to the present invention compensates for variations in process and environmental conditions by using a stable reference clock signal and two matched delay line elements. The delay circuit is capable of delaying an external clock signal by a nominal delay and within narrow tolerances relative to conventional digital delay circuits.
The above and other aspects of the present invention may be carried out in one form by a method for delaying a digital clock signal. The method involves applying a reference clock signal to a reference delay element, applying an input clock signal to an input delay element, where the reference delay element and the input delay element have matching operational characteristics, obtaining, from the reference delay element, information identifying delay characteristics of the reference delay element, and generating a delayed clock signal, based upon the input clock signal, in response to the information.